1. Field of the Invention
This invention relates to a method of recording information in a nonvolatile semiconductor memory.
2. Description of the Related Art
Because nonvolatile semiconductor memories do not require power to retain stored information, the nonvolatile semiconductor memories are used as memories in portable devices and other equipment with low power consumption. One of recent nonvolatile semiconductor memories has a MONOS (Metal Oxide Nitride Oxide Semiconductor) type memory cell structure with two or more gate electrodes (see for example U.S. Pat. No. 5,408,115, U.S. Pat. No. 6,255,166, and Japanese Patent Kokai (Laid-open Application) No. 09-252059). Such MONOS type memory cells include a transistor having an ordinary gate insulating film, and another transistor having another type of gate insulating film (i.e., ONO (Oxide Nitride Oxide)-layered insulating film that can accumulate electric charge). These two transistors are separately provided in a channel formation region of the memory cell.
For the nonvolatile semiconductor memory disclosed in U.S. Pat. No. 5,408,115 and U.S. Pat. No. 6,255,166, it is necessary that the channel density be optimized individually in the channel formation region below the ordinary gate insulating film and below the ONO-layered insulating film. In order to apply separate voltages to the two gate electrodes, voltage generation circuits, decoders, and other peripheral circuitry are necessary for the two gate electrodes respectively. This results in greater device complexity. Further, the mechanism to operate the memory tends to be more complex, and it is difficult to simply and efficiently inject charge into the ONO-layered insulating film.
Because this memory cell structure has at least two gate electrodes and corresponding gate insulating films that contain an ONO-layered insulating film, the memory cell structure is complex, and manufacturing costs are high.
The inventors have already conducted studies on nonvolatile semiconductor memories that would be operated by simpler methods and be manufactured at reduced costs. The inventors filed a patent application in Japan (Japanese Patent Application No. 2003-293648; hereafter referred to as “the preceding application”) covering a portion of the results of these studies.
To aid understanding of the present invention, the structure of nonvolatile semiconductor memory cells disclosed in the preceding application is described below, with reference to FIG. 1 and FIG. 2 of the accompanying drawings.
FIG. 1 is a schematic cross-sectional view of a nonvolatile semiconductor memory cell 100 in the preceding application. A drain region 21 and source region 22, formed by an n+ diffusion layer in the p well 11 formed in a p-type silicon substrate 10, exist separately. Between the drain region 21 and source region 22, a channel formation region 12 is positioned. A gate insulating film 13 is formed on the channel formation region 12, and a gate electrode 30 is formed on the gate insulating film 13. By forming, on the p well 11 of the p-type silicon substrate 10, a gate electrode 30, gate insulating film 13, and drain region 21 and source region 22 of an n+ diffusion layer, the p-type silicon substrate 10 includes an NMOS FET (n-type Metal Oxide Semiconductor Field Effect Transistor).
A first resistance-change portion 23 is formed between the drain region 21 and the channel formation region 12. On the first resistance-change portion 23 is positioned a first charge accumulation portion 50. The first charge accumulation portion 50 includes a silicon oxide film (first oxide film) 41, a silicon nitride film 42, and another silicon oxide film (second oxide film) 43. A second resistance-change portion 26 is provided between the source region 22 and the channel formation region 12. On the second resistance-change portion 26 is positioned a second charge accumulation portion 52. The second charge accumulation portion 52 includes a silicon oxide film (first oxide film) 44, a silicon nitride film 45, and another silicon oxide film (second oxide film) 46.
Hot carriers are injected into the first charge accumulation portion 50 or the second charge accumulation portion 52 to accumulate charge, thereby recording information. That is, by associating a state in which charge is not accumulated and a state in which charge is accumulated with the logical values “0” and “1” or vice versa, one bit of information can be recorded. Whether charge is accumulated in the first charge accumulation portion 50 can be determined by utilizing the following phenomenon. When charge is accumulated in the first charge accumulation portion 50, the resistance of the first resistance-change portion 23 rises, so that the current is reduced, and when charge is not accumulated in the first charge accumulation portion 50, the resistance value of the first resistance-change portion 23 is comparatively low so that the current is increased.
Charge is accumulated by applying a positive voltage to the drain region 21 and gate electrode 30, and setting the source region 22 to ground potential.
The foregoing has described when information is recorded in the first charge accumulation portion 50. Similar description can be applied when information is recorded in the second charge accumulation portion 52. By using a nonvolatile semiconductor memory cell of the preceding application, information can be recorded to and read from each of the first and second charge accumulation portions 50 and 52, so that two bits of information can be recorded to and read from a single nonvolatile semiconductor memory cell. Hence in a memory cell array having a plurality of nonvolatile semiconductor memory cells, the information recording density per unit area can be increased. As a result, the cost of manufacture of a memory cell array necessary for recording the same amount of information can be reduced.
FIG. 2 shows an equivalent circuit diagram of the memory cell 100 shown in FIG. 1. In this circuit, a first resistance-change portion 23 and second resistance-change portion 26 are connected, as variable resistances, to the drain (D) region 21 and source (S) region 22 of the NMOS structure of the memory cell 100.
In the nonvolatile semiconductor memory cell of the preceding application, it is normally necessary that a current of 100 μA or greater flow during charge accumulation. Thus, the power consumption is great. In the nonvolatile semiconductor memory disclosed in Japanese Patent Kokai No. 09-252059, the efficiency of injection of hot carriers is raised by causing a large current to flow. Consequently the power consumption is increased. So, further study is necessary on the problem of large power consumption.